\doxysubsubsubsection{UART Clock Prescaler }
\hypertarget{group___u_a_r_t___clock_prescaler}{}\label{group___u_a_r_t___clock_prescaler}\index{UART Clock Prescaler@{UART Clock Prescaler}}
\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___clock_prescaler_ga7e210157853228d94668b5ee7233087d}{UART\+\_\+\+PRESCALER\+\_\+\+DIV1}}~0x00000000U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___clock_prescaler_gace5f0cc2723defa6e1858d6dd7328146}{UART\+\_\+\+PRESCALER\+\_\+\+DIV2}}~0x00000001U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___clock_prescaler_gab908550eaada50e9abb57e27f2a1b32b}{UART\+\_\+\+PRESCALER\+\_\+\+DIV4}}~0x00000002U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___clock_prescaler_ga39932cc9816584194aec27a1fe5069f4}{UART\+\_\+\+PRESCALER\+\_\+\+DIV6}}~0x00000003U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___clock_prescaler_gaa8243381f97aa0b2c22d3d760c1828fb}{UART\+\_\+\+PRESCALER\+\_\+\+DIV8}}~0x00000004U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___clock_prescaler_ga1e3e467c48fcb55666761454a7412640}{UART\+\_\+\+PRESCALER\+\_\+\+DIV10}}~0x00000005U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___clock_prescaler_gad256f52714b04a7559e8f9176322be92}{UART\+\_\+\+PRESCALER\+\_\+\+DIV12}}~0x00000006U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___clock_prescaler_ga8332f7185809795e77bce091dfd3663c}{UART\+\_\+\+PRESCALER\+\_\+\+DIV16}}~0x00000007U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___clock_prescaler_gaad93948e7d021e2fe44dec073cafcea4}{UART\+\_\+\+PRESCALER\+\_\+\+DIV32}}~0x00000008U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___clock_prescaler_gada8fd9635ead84946cf45aa4bf3f682e}{UART\+\_\+\+PRESCALER\+\_\+\+DIV64}}~0x00000009U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___clock_prescaler_gac111f3090e35143688710114e1e9be6d}{UART\+\_\+\+PRESCALER\+\_\+\+DIV128}}~0x0000000\+AU
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___clock_prescaler_ga0d602ff1d466e94c5ebe85c2e9e36d11}{UART\+\_\+\+PRESCALER\+\_\+\+DIV256}}~0x0000000\+BU
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}


\label{doc-define-members}
\Hypertarget{group___u_a_r_t___clock_prescaler_doc-define-members}
\doxysubsubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___u_a_r_t___clock_prescaler_ga7e210157853228d94668b5ee7233087d}\index{UART Clock Prescaler@{UART Clock Prescaler}!UART\_PRESCALER\_DIV1@{UART\_PRESCALER\_DIV1}}
\index{UART\_PRESCALER\_DIV1@{UART\_PRESCALER\_DIV1}!UART Clock Prescaler@{UART Clock Prescaler}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_PRESCALER\_DIV1}{UART\_PRESCALER\_DIV1}}
{\footnotesize\ttfamily \label{group___u_a_r_t___clock_prescaler_ga7e210157853228d94668b5ee7233087d} 
\#define UART\+\_\+\+PRESCALER\+\_\+\+DIV1~0x00000000U}

fclk\+\_\+pres = fclk \Hypertarget{group___u_a_r_t___clock_prescaler_ga1e3e467c48fcb55666761454a7412640}\index{UART Clock Prescaler@{UART Clock Prescaler}!UART\_PRESCALER\_DIV10@{UART\_PRESCALER\_DIV10}}
\index{UART\_PRESCALER\_DIV10@{UART\_PRESCALER\_DIV10}!UART Clock Prescaler@{UART Clock Prescaler}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_PRESCALER\_DIV10}{UART\_PRESCALER\_DIV10}}
{\footnotesize\ttfamily \label{group___u_a_r_t___clock_prescaler_ga1e3e467c48fcb55666761454a7412640} 
\#define UART\+\_\+\+PRESCALER\+\_\+\+DIV10~0x00000005U}

fclk\+\_\+pres = fclk/10 \Hypertarget{group___u_a_r_t___clock_prescaler_gad256f52714b04a7559e8f9176322be92}\index{UART Clock Prescaler@{UART Clock Prescaler}!UART\_PRESCALER\_DIV12@{UART\_PRESCALER\_DIV12}}
\index{UART\_PRESCALER\_DIV12@{UART\_PRESCALER\_DIV12}!UART Clock Prescaler@{UART Clock Prescaler}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_PRESCALER\_DIV12}{UART\_PRESCALER\_DIV12}}
{\footnotesize\ttfamily \label{group___u_a_r_t___clock_prescaler_gad256f52714b04a7559e8f9176322be92} 
\#define UART\+\_\+\+PRESCALER\+\_\+\+DIV12~0x00000006U}

fclk\+\_\+pres = fclk/12 \Hypertarget{group___u_a_r_t___clock_prescaler_gac111f3090e35143688710114e1e9be6d}\index{UART Clock Prescaler@{UART Clock Prescaler}!UART\_PRESCALER\_DIV128@{UART\_PRESCALER\_DIV128}}
\index{UART\_PRESCALER\_DIV128@{UART\_PRESCALER\_DIV128}!UART Clock Prescaler@{UART Clock Prescaler}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_PRESCALER\_DIV128}{UART\_PRESCALER\_DIV128}}
{\footnotesize\ttfamily \label{group___u_a_r_t___clock_prescaler_gac111f3090e35143688710114e1e9be6d} 
\#define UART\+\_\+\+PRESCALER\+\_\+\+DIV128~0x0000000\+AU}

fclk\+\_\+pres = fclk/128 \Hypertarget{group___u_a_r_t___clock_prescaler_ga8332f7185809795e77bce091dfd3663c}\index{UART Clock Prescaler@{UART Clock Prescaler}!UART\_PRESCALER\_DIV16@{UART\_PRESCALER\_DIV16}}
\index{UART\_PRESCALER\_DIV16@{UART\_PRESCALER\_DIV16}!UART Clock Prescaler@{UART Clock Prescaler}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_PRESCALER\_DIV16}{UART\_PRESCALER\_DIV16}}
{\footnotesize\ttfamily \label{group___u_a_r_t___clock_prescaler_ga8332f7185809795e77bce091dfd3663c} 
\#define UART\+\_\+\+PRESCALER\+\_\+\+DIV16~0x00000007U}

fclk\+\_\+pres = fclk/16 \Hypertarget{group___u_a_r_t___clock_prescaler_gace5f0cc2723defa6e1858d6dd7328146}\index{UART Clock Prescaler@{UART Clock Prescaler}!UART\_PRESCALER\_DIV2@{UART\_PRESCALER\_DIV2}}
\index{UART\_PRESCALER\_DIV2@{UART\_PRESCALER\_DIV2}!UART Clock Prescaler@{UART Clock Prescaler}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_PRESCALER\_DIV2}{UART\_PRESCALER\_DIV2}}
{\footnotesize\ttfamily \label{group___u_a_r_t___clock_prescaler_gace5f0cc2723defa6e1858d6dd7328146} 
\#define UART\+\_\+\+PRESCALER\+\_\+\+DIV2~0x00000001U}

fclk\+\_\+pres = fclk/2 \Hypertarget{group___u_a_r_t___clock_prescaler_ga0d602ff1d466e94c5ebe85c2e9e36d11}\index{UART Clock Prescaler@{UART Clock Prescaler}!UART\_PRESCALER\_DIV256@{UART\_PRESCALER\_DIV256}}
\index{UART\_PRESCALER\_DIV256@{UART\_PRESCALER\_DIV256}!UART Clock Prescaler@{UART Clock Prescaler}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_PRESCALER\_DIV256}{UART\_PRESCALER\_DIV256}}
{\footnotesize\ttfamily \label{group___u_a_r_t___clock_prescaler_ga0d602ff1d466e94c5ebe85c2e9e36d11} 
\#define UART\+\_\+\+PRESCALER\+\_\+\+DIV256~0x0000000\+BU}

fclk\+\_\+pres = fclk/256 \Hypertarget{group___u_a_r_t___clock_prescaler_gaad93948e7d021e2fe44dec073cafcea4}\index{UART Clock Prescaler@{UART Clock Prescaler}!UART\_PRESCALER\_DIV32@{UART\_PRESCALER\_DIV32}}
\index{UART\_PRESCALER\_DIV32@{UART\_PRESCALER\_DIV32}!UART Clock Prescaler@{UART Clock Prescaler}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_PRESCALER\_DIV32}{UART\_PRESCALER\_DIV32}}
{\footnotesize\ttfamily \label{group___u_a_r_t___clock_prescaler_gaad93948e7d021e2fe44dec073cafcea4} 
\#define UART\+\_\+\+PRESCALER\+\_\+\+DIV32~0x00000008U}

fclk\+\_\+pres = fclk/32 \Hypertarget{group___u_a_r_t___clock_prescaler_gab908550eaada50e9abb57e27f2a1b32b}\index{UART Clock Prescaler@{UART Clock Prescaler}!UART\_PRESCALER\_DIV4@{UART\_PRESCALER\_DIV4}}
\index{UART\_PRESCALER\_DIV4@{UART\_PRESCALER\_DIV4}!UART Clock Prescaler@{UART Clock Prescaler}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_PRESCALER\_DIV4}{UART\_PRESCALER\_DIV4}}
{\footnotesize\ttfamily \label{group___u_a_r_t___clock_prescaler_gab908550eaada50e9abb57e27f2a1b32b} 
\#define UART\+\_\+\+PRESCALER\+\_\+\+DIV4~0x00000002U}

fclk\+\_\+pres = fclk/4 \Hypertarget{group___u_a_r_t___clock_prescaler_ga39932cc9816584194aec27a1fe5069f4}\index{UART Clock Prescaler@{UART Clock Prescaler}!UART\_PRESCALER\_DIV6@{UART\_PRESCALER\_DIV6}}
\index{UART\_PRESCALER\_DIV6@{UART\_PRESCALER\_DIV6}!UART Clock Prescaler@{UART Clock Prescaler}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_PRESCALER\_DIV6}{UART\_PRESCALER\_DIV6}}
{\footnotesize\ttfamily \label{group___u_a_r_t___clock_prescaler_ga39932cc9816584194aec27a1fe5069f4} 
\#define UART\+\_\+\+PRESCALER\+\_\+\+DIV6~0x00000003U}

fclk\+\_\+pres = fclk/6 \Hypertarget{group___u_a_r_t___clock_prescaler_gada8fd9635ead84946cf45aa4bf3f682e}\index{UART Clock Prescaler@{UART Clock Prescaler}!UART\_PRESCALER\_DIV64@{UART\_PRESCALER\_DIV64}}
\index{UART\_PRESCALER\_DIV64@{UART\_PRESCALER\_DIV64}!UART Clock Prescaler@{UART Clock Prescaler}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_PRESCALER\_DIV64}{UART\_PRESCALER\_DIV64}}
{\footnotesize\ttfamily \label{group___u_a_r_t___clock_prescaler_gada8fd9635ead84946cf45aa4bf3f682e} 
\#define UART\+\_\+\+PRESCALER\+\_\+\+DIV64~0x00000009U}

fclk\+\_\+pres = fclk/64 \Hypertarget{group___u_a_r_t___clock_prescaler_gaa8243381f97aa0b2c22d3d760c1828fb}\index{UART Clock Prescaler@{UART Clock Prescaler}!UART\_PRESCALER\_DIV8@{UART\_PRESCALER\_DIV8}}
\index{UART\_PRESCALER\_DIV8@{UART\_PRESCALER\_DIV8}!UART Clock Prescaler@{UART Clock Prescaler}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_PRESCALER\_DIV8}{UART\_PRESCALER\_DIV8}}
{\footnotesize\ttfamily \label{group___u_a_r_t___clock_prescaler_gaa8243381f97aa0b2c22d3d760c1828fb} 
\#define UART\+\_\+\+PRESCALER\+\_\+\+DIV8~0x00000004U}

fclk\+\_\+pres = fclk/8 